Modeling of interconnect capacitance, delay, and crosstalk in VLSI

TLDR

Metal interconnects increasingly dominate performance in complex VLSI circuits. The paper develops closed‑form capacitance formulas for parallel lines on a plane and wires between two planes, accounting for flux to adjacent wires and ground. It also derives closed‑form expressions for delay and crosstalk noise based on these capacitance models. The capacitance, delay, and crosstalk models closely match 3‑D Poisson solutions, measurement data, and SPICE simulations.

Abstract

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations.