Nanoscale Research Letters · 2015 · 88 citations · 59 references
EngineeringMaterials EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor MaterialsComplementary Metal-oxide-semiconductor TechnologyDevice ReliabilityElectrode MaterialsMemory DevicesMemristive MaterialsSemiconductor Device MaterialsComplementary Metal-oxide-semiconductor DevicesData RetentionEnduranceFilamentary Switching MechanismsMemory MaterialsMemristive MemoryResistive Random-access MemoryResistive Switching Materials
The performances of conductive-bridging random access memory (CBRAM) have been reviewed for different switching materials such as chalcogenides, oxides, and bilayers in different structures. The structure consists of an inert electrode and one oxidized electrode of copper (Cu) or silver (Ag). The switching mechanism is the formation/dissolution of a metallic filament in the switching materials under external bias. However, the growth dynamics of the metallic filament in different switching materials are still debated. All CBRAM devices are switching under an operation current of 0.1 μA to 1 mA, and an operation voltage of ±2 V is also needed. The device can reach a low current of 5 pA; however, current compliance-dependent reliability is a challenging issue. Although a chalcogenide-based material has opportunity to have better endurance as compared to an oxide-based material, data retention and integration with the complementary metal-oxide-semiconductor (CMOS) process are also issues. Devices with bilayer switching materials show better resistive switching characteristics as compared to those with a single switching layer, especially a program/erase endurance of >10(5) cycles with a high speed of few nanoseconds. Multi-level cell operation is possible, but the stability of the high resistance state is also an important reliability concern. These devices show a good data retention of >10(5) s at >85°C. However, more study is needed to achieve a 10-year guarantee of data retention for non-volatile memory application. The crossbar memory is benefited for high density with low power operation. Some CBRAM devices as a chip have been reported for proto-typical production. This review shows that operation current should be optimized for few microamperes with a maintaining speed of few nanoseconds, which will have challenges and also opportunities for three-dimensional (3D) architecture.
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