1989 · 10 citations · 1 references
EngineeringComputer EngineeringComputer SystemsComputer ArchitectureDesign AutomationSystem-on-chip DesignDesign HierarchyHierarchical DesignLogic SynthesisPhysical DesignStandard Cell DesignVery-large-scale Integration LayoutCell Layout DesignConfigurable Logic Cell DesignGate-level ModelingLogic Cell DesignMacro PlacementMulti-level Logic DesignMulti-level Logic SynthesisStandard Cell Placement
A parameterizable generator that can generate macrocells with multilevel hierarchies is described. High-density macrocells that incorporate random logic can be laid out automatically. The system generates full-custom macrocell layouts, sea-of-gates masterslice layouts, standard cell descriptions for such macrocells, and equivalent logic and function models for chip-level simulations
1
A BiCMOS channelless masterslice with on-chip voltage converter
Hiroya Fukuda, S. Horiguchi, M. Urano et al. · 2003 · 17 citations
Engineering, Computer Engineering, Electrical Engineering +17