Standard Cell Placement

Standard Cell Placement is a layout optimization methodology in Very-Large-Scale Integration design that determines the optimal positions of pre-characterized logic cells within a fixed-height row structure to minimize area, wirelength, and timing delay while adhering to design rules and routing constraints.

349

Publications

15.7K

Citations

716

Authors

186

Institutions

Publications per year

2017–2026

45

Authors

716

  1. DZ
    David Z. Pan

    The University of Texas at Austin, United States

    18 publications · 502 citations

    14

    h-index

  2. AB
    Andrew B. Kahng

    University of California San Diego, United States

    18 publications · 1.2K citations

    14

    h-index

  3. YC
    Yao‐Wen Chang

    National Taiwan University, Taiwan

    15 publications · 448 citations

    14

    h-index

  4. BY
    Bei Yu

    Chinese University of Hong Kong, Hong Kong SAR China

    12 publications · 388 citations

    11

    h-index

  5. MD
    Martin D. F. Wong

    University of Illinois Urbana-Champaign, United States

    13 publications · 278 citations

    11

    h-index

1–5 of 716

Venues

  1. 31

    h-index

  2. Design Automation Conference

    Conference · 11 publications · 525 citations

    11

    h-index

  3. International Conference on Computer Aided Design

    Conference · 11 publications · 297 citations

    10

    h-index

  4. 10

    h-index

  5. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 6 publications · 261 citations

    6

    h-index

1–5