Standard Cell Placement
Standard Cell Placement is a layout optimization methodology in Very-Large-Scale Integration design that determines the optimal positions of pre-characterized logic cells within a fixed-height row structure to minimize area, wirelength, and timing delay while adhering to design rules and routing constraints.
349
Publications
15.7K
Citations
716
Authors
186
Institutions
Publications per year
2017–2026
45
349
Security analysis of integrated circuit camouflaging
Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu et al. · 2013 · 379 citations
1–5 of 349
716
14
h-index
14
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14
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11
h-index
University of Illinois Urbana-Champaign, United States
13 publications · 278 citations
11
h-index
1–5 of 716
186
University of Illinois Urbana-Champaign
Urbana, United States
20 h-index
63 publications
2.3K citations
University of California San Diego
San Diego, United States
16 h-index
45 publications
2.1K citations

National Taiwan University
Taipei, Taiwan
15 h-index
40 publications
1.2K citations
The University of Texas at Austin
Austin, United States
14 h-index
54 publications
1.5K citations
University of California, Los Angeles
Los Angeles, United States
14 h-index
37 publications
2.5K citations
Cadence Design Systems (United States)
San Jose, United States
13 h-index
38 publications
2.7K citations
University of Michigan
Ann Arbor, United States
11 h-index
25 publications
1.1K citations
University of California, Berkeley
Berkeley, United States
11 h-index
20 publications
2.7K citations
1–8 of 186
47 publications · 3.5K citations
31
h-index
Conference · 11 publications · 525 citations
11
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Conference · 11 publications · 297 citations
10
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11 publications · 205 citations
10
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TODAES · 6 publications · 261 citations
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1–5