Modeling and sizing for minimum energy operation in subthreshold circuits

TLDR

Subthreshold operation is emerging as an energy‑saving approach to many energy‑constrained applications where processor speed is less important. The study develops analytical solutions for optimal supply and threshold voltages and sizing to minimize energy in subthreshold circuits. The authors derive analytical expressions for optimal VDD and VT and validate them with a 0.18‑µm test chip that compares normal sizing to energy‑minimizing sizing. The results reveal that optimum VDD varies with design and operating conditions, that minimum‑sized devices theoretically minimize energy, and that standard‑cell libraries already achieve near‑optimal energy savings.

Abstract

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V/sub DD/ and V/sub T/ to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-/spl mu/m test chip is used to compare normal sizing and sizing to minimize operational V/sub DD/ and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.