Concepedia

Multi-level Logic Synthesis

Multi-Level Logic Synthesis is a logic synthesis methodology that optimizes digital circuits by representing and transforming Boolean functions into multi-level networks of logic gates, distinguished from flat two-level forms through hierarchical decomposition and technology-independent simplification.

242

Publications

11.1K

Citations

408

Authors

163

Institutions

Publications per year

2017–2026

18

Parents

Publications

242

MIS: A Multiple-Level Logic Optimization System

Robert K. Brayton, Richard Rudell, Alberto Sangiovanni‐Vincentelli et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 1.2K citations

, , +16

Multiple-Valued Logic—its Status and its Future

Hurst · IEEE Transactions on Computers · 1984 · 601 citations

, , +15

Logic verification using binary decision diagrams in a logic synthesis environment

Sharad Malik, A.R. Wang, Robert K. Brayton et al. · 2003 · 509 citations

, , +17

Multiple-Valued Minimization for PLA Optimization

Richard Rudell, Alberto Sangiovanni‐Vincentelli · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 429 citations

, , +17

Multilevel logic synthesis

Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni‐Vincentelli · Proceedings of the IEEE · 1990 · 412 citations

, , +17

1–5 of 242

Authors

408

  1. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    21 publications · 2.8K citations

    17

    h-index

  2. MP
    Marek Perkowski

    Portland State University, United States

    11 publications · 296 citations

    11

    h-index

  3. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    11 publications · 3K citations

    11

    h-index

  4. AM
    Alan Mishchenko

    University of California, Berkeley, United States

    10 publications · 224 citations

    10

    h-index

  5. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    7 publications · 234 citations

    7

    h-index

1–5 of 408

Institutions

163

  1. University of California, Berkeley

    Berkeley, United States

    23 h-index

    88 publications

    12.3K citations

  2. Portland State University

    Portland, United States

    12 h-index

    22 publications

    613 citations

  3. University of Illinois Urbana-Champaign

    Urbana, United States

    11 h-index

    18 publications

    595 citations

  4. Fujitsu (Japan)

    Kawasaki, Japan

    9 h-index

    22 publications

    1.5K citations

  5. École Polytechnique Fédérale de Lausanne

    Lausanne, Switzerland

    9 h-index

    27 publications

    770 citations

  6. Princeton University

    Princeton, United States

    8 h-index

    17 publications

    609 citations

  7. Eindhoven University of Technology

    Eindhoven, The Netherlands

    7 h-index

    12 publications

    182 citations

  8. Silesian University of Technology

    Gliwice, Poland

    6 h-index

    10 publications

    244 citations

1–8 of 163

Venues

  1. 18

    h-index

  2. IEEE Transactions on Computers

    12 publications · 1K citations

    11

    h-index

  3. VLSI design

    4 publications · 108 citations

    4

    h-index

  4. Design Automation Conference

    Conference · 4 publications · 89 citations

    4

    h-index

  5. International Conference on Computer Aided Design

    Conference · 3 publications · 108 citations

    3

    h-index

1–5