Macro Placement
Macro Placement is a physical design task that involves determining the optimal positions of large functional blocks within a chip layout to minimize interconnect length and congestion while adhering to design constraints.
114
Publications
4.9K
Citations
267
Authors
85
Institutions
Publications per year
2017–2026
16
Parents
114
Tung-Chieh Chen, Zhewei Jiang, Tien-Chang Hsu et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 344 citations
Unification of partitioning, placement and floorplanning
Saurabh Adya, Shashank Chaturvedi, Jarrod A. Roy et al. · 2005 · 170 citations
Jingwei Lu, Pengwen Chen, Chin-Chih Chang et al. · ACM Transactions on Design Automation of Electronic Systems · 2015 · 158 citations
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85

National Taiwan University
Taipei, Taiwan
16 h-index
58 publications
3.7K citations
University of Michigan
Ann Arbor, United States
11 h-index
24 publications
1.8K citations
University of California, Los Angeles
Los Angeles, United States
7 h-index
15 publications
592 citations
University of California, Berkeley
Berkeley, United States
6 h-index
17 publications
979 citations
IBM Research - Austin
Austin, United States
6 h-index
23 publications
655 citations
University of Illinois Urbana-Champaign
Urbana, United States
6 h-index
13 publications
552 citations
Yale University
New Haven, United States
5 h-index
7 publications
561 citations
The University of Texas at Austin
Austin, United States
4 h-index
15 publications
648 citations
1–8 of 85
14 publications · 1.1K citations
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ICCAD · 3 publications · 131 citations
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TODAES · 3 publications · 259 citations
3
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Conference · 2 publications · 62 citations
2
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Conference · 2 publications · 79 citations
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