A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Abstract

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.