A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line

Abstract

This paper describes the key technologies used in a 1-Gb synchronous DRAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (V/sub ss/) precharged bit line with a negative word-line reset scheme enables a nonboosted 2.1-V word-line architecture. Total power consumption is less than that of the conventional half-V/sub cc/ precharged bit-line scheme. We also propose a vernier-type, high-accuracy delay-locked-loop circuit realizing /spl plusmn/20-ps quantization errors for clock recovery and skew elimination.