250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture

Abstract

A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.