A 150 MHz 8-banks 256 Mb synchronous DRAM with wave pipelining methods

Abstract

A 256 Mb synchronous DRAM with 8 banks of 32 Mb arrays introduces (1) post charge logic in the critical timing paths, (2) a wave pipelining in the data path and (3) hierarchical I/O architecture. This simplifies the latency control and leads to a fully-synchronous operation to the external clock at 150 MHz.