IEEE Electron Device Letters · 2011 · 60 citations · 8 references
EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsMicrowave EngineeringChip PackagingIntegrated Circuit DesignMicrowave Device SimulationMicrowave Integrated CircuitsMicrowave PackagingRadio-frequency Integrated CircuitsGainInsertion LossPackage ParasiticsParasitic EffectsParasitic ExtractionRadio-frequency PackagingReturn LossThree-dimensional Integration
This letter reports on techniques of full-wave extractions and analytical calculations to investigate the through-strata-via (TSV) parasitics in 3-D integration/packaging. Both methods suggest close TSV RLGC results over the entire frequency range of interest. A wideband SPICE model is generated from the TSV electromagnetic solutions with good agreement for both magnitudes and phases of return loss and insertion loss. Further sensitivity analysis results indicate that the isolation layer thickness weighs most in the signal gain at 20 GHz. This letter provides some insight to TSV electrical characteristics and helps TSV physical design to maximize the benefits of 3-D systems.
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H.A. Wheeler · Proceedings of the IRE · 1942 · 749 citations
Three-dimensional silicon integration
John Knickerbocker, Paul Andry, B. Dang et al. · IBM Journal of Research and Development · 2008 · 493 citations
Engineering, Electrical Engineering, Manufacturing Engineering +17