IEEE Design & Test of Computers · 1993 · 11 citations · 5 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designSystem-on-chip DesignBuilt-in Self-testConfigurable Logic BlocksDesign For TestabilityEmbedded DebuggingHardware DebuggingSelf-checking CircuitsDebuggingEmbedded TestObservabilityOverhead ReductionPerformance OverheadScan DesignSelf-checking DesignTestability
CrossCheck, an approach to the application-specific integrated circuit ASIC test problem that is based on embedding test structures into the base array of the ASIC, is discussed. With a specially designed storage element called the cross-controlled latch, CrossCheck combines controllability and observability to produce a highly testable ASIC having minimal area and performance overhead. CrossCheck is a designer-transparent solution that imposes none of the rules and restrictions of other design-for-testability (DFT) methodologies. In CrossCheck, test structures are embedded into the ASIC base, rather than added by the designer to the schematic as with scan or built-in self-test (BIST) methodologies. The built-in observability also offers easier debugging and diagnostics methods to the designer. Experimental results that demonstrate the potential of the CrossCheck method on a broad range of ASIC styles and sizes are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Design for testability—A survey
T.W. Williams, Kenneth P. Parker · Proceedings of the IEEE · 1983 · 393 citations
ATPG based on a novel grid-addressable latch element
S.J. Chandra, Tom Ferry, T. Gheewala et al. · 1991 · 28 citations