Self-checking Design

Self-Checking Design is a circuit-level methodology in digital system design that belongs to the class of fault-tolerant techniques, distinguished by its ability to concurrently detect internal faults through intrinsic redundancy and built-in error-checking mechanisms without requiring external test equipment.

267

Publications

8.8K

Citations

396

Authors

173

Institutions

Publications per year

2017–2026

16

Authors

396

  1. CM
    Cecilia Metra

    University of Bologna, Italy

    22 publications · 541 citations

    14

    h-index

  2. MF
    M. Favalli

    University of Bologna, Italy

    13 publications · 332 citations

    12

    h-index

  3. BR
    B. Riccò

    University of Bologna, Italy

    11 publications · 265 citations

    11

    h-index

  4. MN
    M. Nicolaidis

    Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France

    10 publications · 483 citations

    10

    h-index

  5. EM
    E.J. McCluskey

    Stanford University, United States

    11 publications · 389 citations

    10

    h-index

1–5 of 396

Venues

  1. IEEE Transactions on Computers

    50 publications · 2.1K citations

    26

    h-index

  2. 10

    h-index

  3. 8

    h-index

  4. IEEE Journal of Solid-State Circuits

    7 publications · 220 citations

    7

    h-index

  5. Journal of Electronic Testing

    JETTA · 8 publications · 247 citations

    7

    h-index

1–5