Partial-SOI isolation structure for reduced bipolar transistor parasitics

Abstract

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>