Sub-30ps ECL circuits using high-f/sub T/ Si and SiGe epitaxial base SEEW transistors

Abstract

A high-performance bipolar technology is presented which involves Si and SiGe epitaxial base formation in a selective epitaxy emitter window (SEEW) structure. Si transistors have cut-off frequencies (f/sub T/) of 35-53 GHz while the f/sub T/ of SiGe devices ranges from 45 GHz to 63 GHz. The SEEW structure allowed emitter width reduction to 0.35 mu m using optical lithography with 0.8 mu m minimum linewidth to operate the device at high current density near maximum f/sub T/. The ECL (emitter coupled logic) gate delay is examined as function of the trade-off between f/sub T/ and intrinsic base resistance and of the main device parasitics, i.e., base resistance and collector-base capacitance. A minimum ECL gate delay of 24.3 ps was realized in an unloaded ECL ring oscillator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>