Fully depleted 20-nm SOI CMOSFETs with W-clad gate/source/drain layers

Abstract

Fully-depleted 20-nm SOI complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) were successfully fabricated without a raised source/drain (S/D) structure, instead using low-temperature selective tungsten CVD (SWCVD) technology that can reduce the S/D series resistance. The thickness of the residual SOI layer under the W-clad layer in the S/D region was 6 nm for an nMOSFET and 9 nm for a pMOSFET. For 0.15-/spl mu/m-gate CMOSFETs, the subthreshold swings were 70 and 75 mV/dec for the nMOSFET and pMOSFET, respectively. The effectiveness of SWCVD technology when applied to ultrathin SOI devices was confirmed by small Si consumption and good continuity between the W and SOI layers. We expect that the S/D series resistance can be reduced to less than 1 k/spl Omega/-/spl mu/m by optimizing the S/D implantation conditions.