IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2002 · 29 citations · 8 references
EngineeringElectrical EngineeringPackaging DesignSemiconductor DevicesSemiconductor MaterialsChip PackagingPackaging EngineeringPackaging MaterialsPlastic PackagingWide-bandgap Semiconductor DevicesWide-bandgap SemiconductorsBandgap ReferencesBandgap Voltage ReferencesPlanarizationPlanarization TechniquesPositive Temperature CoefficientProcess-induced StressesThermo-mechanical StressThermomechanical Stress
Bandgap references, packaged in plastic, have been known to shift in voltage, a pre-package to post-package voltage variation. This package shift has been analytically discussed and experimentally investigated in this paper. The culprits for such a variation are the package-induced stresses present once the reference is encapsulated. Systematic voltage shifts can range from -3 to -7 mV, and is closely related to package type and processing. Major emphasis has been placed on reducing the random package-shift component, since systematic package shift can be trimmed and its temperature coefficient compensated. The package shift is seen to have a systematic positive temperature coefficient; its effects are mitigated as temperature increases. In summary, results of the study show that die-surface planarization techniques and mechanically elastic compliant layers between the die and the package reduce random as well as systematic package shifts. In particular, systematic variations improved from -5 to -2 mV (0.4% to 0.17% bandgap error) and three-sigma (3/spl sigma/) variations improved from 8 to 4 mV (0.67% to 0.33% bandgap error) when adding a 15-/spl mu/m mechanically compliant layer between the die and the package.
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Analysis and Design of Analog Integrated Circuits
W.R. Betts · Electronics and Power · 1978 · 3.8K citations
CMOS stress sensors on [100] silicon
R.C. Jaeger, Jeffrey C. Suhling, R. Ramani et al. · IEEE Journal of Solid-State Circuits · 2000 · 176 citations