Threading a multiple scan paths in a VLSI circuit

Abstract

The problem of configurating multiple scan paths in a VLSI circuit is discussed. Based on the analysis of the circuit, certain specific subcircuits are identified and a scan path is next configured for testing each such subcircuit. Rather than the algorithmic approach, a knowledge-based system strategy has been adopted to automate the approach taken by a human designer to tackle the problem.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>