On the impact of spatial parametric variations on MOS transistor mismatch

Abstract

Quite often, especially during the development of advanced MOS fabrication processes, it is observed that for matched-pair MOS transistors with large device dimensions the general mismatch law "/spl sigma/(/spl Delta/P)=A/sub P///spl radic/(area)" (or its derivatives) does not always hold. This paper demonstrates that an explanation for this effect can be found in the presence of non-random parameter distributions over a wafer (referred to as spatial parametric variations). Furthermore, the use of a dedicated test structure to distinguish between random and non-random mismatch causes is presented.