2003 · 28 citations · 7 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsSemiconductor DevicesVlsi DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsSemiconductor Device MaterialsWide-bandgap Semiconductor DevicesWide-bandgap SemiconductorsCmos Fabrication ProcessesCurrent DensityElectron MobilityGate Oxide InterfacesGate OxidesInversion Layer FormationNitric OxideShadow Mask Patterning
We report the design and fabrication of UMOSFETs on 4H-SiC with specific on-resistances of 105.1 m/spl Omega/ cm/sup 2/ at a current density of 100 A/cm/sup 2/ and blocking voltage of 5,050 V. These devices incorporate an extended self-aligned p-bottom implant to protect the gate oxide from high electric fields. A novel shadow implant mask was developed to shield the sidewalls from any unwanted p-bottom implant. These UMOSFETs are also the first to incorporate a post-oxidation anneal (POA) in nitric oxide (NO) to improve the inversion layer electron mobility. A single zone JTE (junction termination extension) with peak blocking voltage of 7,500 V was implemented in the device design.
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Physics of Semiconductor Devices
Samarth Jain, S. Radhakrishna · 1987 · 4.2K citations
4.5 kV novel high voltage high performance SiC-FET "SIAFET"
Y. Sugawara, Masafumi Asano, Ranbir Singh et al. · 2002 · 23 citations