2002 · 15 citations · 2 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMicroelectronicsSystem-on-chip DesignMemory DevicesMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignMicroarchitecture DesignProcessor MicroarchitectureCache MemoryCache Memory DesignHigh Bandwidth MemoryMemory Controller DesignMemory Interface ArchitectureMemory Interface DesignOn-chip Memory DesignRisc Architectures
The M32R/D is a 32-bit microprocessor with on-chip 2M-byte (16M-bit) DRAM. It has a 32-bit RISC CPU, 32-bit/spl times/16-bit multiply and accumulator, 2M-byte DRAM, 2K-byte cache memory, and a memory controller. The CPU, DRAM, and cache memory are connected with a 128-bit 66.6MHz internal bus. This wide internal bus allows high speed transfer of instructions. The use of a 128-bit bus resulted in a 13% improvement in performance as compared with 32-bit bus.
2
A concurrent operating CDRAM for low cost multi-media
A 90 MHz 16 Mbit system integrated memory with direct interface to CPU
K. Dosaka, Akira Yamazaki, Naoya Watanabe et al. · 2002 · 10 citations