2002 · 10 citations · 3 references
EngineeringComputer EngineeringComputer SystemsComputer ArchitectureMemoryMicroelectronicsIntegrated Circuit DesignLow-power Cache DesignMemory DevicesMemory HierarchyMemory ManagementMemory Subsystem DesignEmbedded MemoryEmbedded Memory IntegrationMemory Circuit DesignMemory Interface ArchitectureMemory Interface DesignMemory Interface Integration
This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM and control circuitry including a TAG. This system memory realizes a computer system without glue chips. Thus, this system memory brings a computer system which is low cost, low power and compact size with sufficient performance. The maximum operating frequency is 90 MHz and the operating current at cache hit is 156 mA.
3
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme
K. Dosaka, Y. Konishi, K. Hayano et al. · IEEE Journal of Solid-State Circuits · 1992 · 19 citations
A 100 MHz 4 Mb cache DRAM with fast copy-back scheme
K. Dosaka, Y. Konishi, K. Hayano et al. · 2003 · 18 citations
A concurrent operating CDRAM for low cost multi-media