Memory Interface Architecture
Memory Interface Architecture is a specialized framework within I/O architecture that defines the structural and operational principles governing data exchange between a processing unit and memory subsystems, distinguished by its focus on protocols, bandwidth management, latency optimization, and signal integrity specific to memory access and control.
152
Publications
6.3K
Citations
759
Authors
158
Institutions
Publications per year
2017–2026
16
Parents
152
The design and implementation of a first-generation CELL processor
D. Pham, S. Asano, M. Bolliger et al. · 2005 · 547 citations
Engineering, Computer Engineering, Electrical Engineering +17
Naga K. Govindaraju, Jim Gray, Ritesh Kumar et al. · 2006 · 422 citations
Synchronization and communication in the T3E multiprocessor
Steven L. Scott · 1996 · 269 citations · Full text
Power7: IBM's Next-Generation Server Processor
Balaram Sinharoy, William J. Starke, Michael S. Floyd · IEEE Micro · 2010 · 231 citations
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158
Rambus (United States)
Sunnyvale, United States
10 h-index
133 publications
4.9K citations
Samsung (South Korea)
Seoul, South Korea
9 h-index
64 publications
1.3K citations
IBM (United States)
Armonk, United States
7 h-index
58 publications
6.3K citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
6 h-index
10 publications
341 citations
University of California, Los Angeles
Los Angeles, United States
5 h-index
22 publications
477 citations
Princeton University
Princeton, United States
5 h-index
18 publications
921 citations
NEC (Japan)
Tokyo, Japan
5 h-index
29 publications
472 citations

University of Bologna
Bologna, Italy
4 h-index
8 publications
148 citations
1–8 of 158
15 publications · 664 citations
13
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4 publications · 168 citations
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3 publications · 78 citations
3
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Repository · 3 publications · 81 citations
3
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2 publications · 275 citations
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