J. Keaty - Concepedia

Concepedia

Author

J. Keaty

IBM Research - Austin

Also Known As

J. Keaty, J. M. Keaty, J.M. Keaty, John Keaty, John M. Keaty

10

Publications

1.2K

Citations

9

H-Index

32

Concepts

All Affiliations

IBM Research - Austin IBM (United States)Toshiba (Japan)Toshiba (United States)IBM Research - Thomas J. Watson Research Center

JK

About

J. Keaty is an author at IBM Research - Austin specializing in microelectronics, electrical engineering, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	1.2K
2	Computer Engineering	9	9	1.2K
3	Electrical Engineering	9	9	1.2K
4	Systems Engineering	2	2	148
5	Computer Science	1	1	546

J. Keaty

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9

Publications

1.2K

Citations

9

H-Index

	Year	Citations
The design and implementation of a first-generation CELL processor D. Pham, S. Asano, M. Bolliger, EngineeringVlsi DesignPower Architecture ProcessorComputer ArchitectureProcessor Architecture	2005	546
Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor D. Pham, T. Aipperspach, D. Boerstler, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignPhysical ImplementationComputer ArchitectureProcessor Architecture	2005	236
Physical design of a fourth-generation POWER GHz microprocessor C.J. Anderson, John G. Petrovick, J. Keaty, EngineeringVlsi DesignRadio FrequencyOff-chip L3Physical Design	2002	117
The circuit and physical design of the POWER4 microprocessor J.D. Warnock, J. Keaty, John G. Petrovick, IBM Journal of Research and Development EngineeringElectronic DesignComputer ArchitecturePower ElectronicsHardware Security	2002	116
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor S.C. Chan, P.J. Restle, T. Bucelot, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignEnergy EfficiencyComputer ArchitecturePower Electronics	2009	51
The design and implementation of a first-generation CELL processor - a multi-core SoC D. Pham, S. Asano, M. Bolliger, Memory Interface ControllerEngineeringComputer ArchitectureProcessor ArchitectureFirst-generation Cell	2005	32
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor Steven H. Chan, P.J. Restle, T. Bucelot, Electrical EngineeringLc Tank NetworkGlobal Clock PowerVlsi DesignEngineering	2008	23
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC D. Pham, E. Behnen, M. Bolliger, EngineeringVlsi DesignComputer ArchitectureProcessor ArchitectureHardware Architecture	2006	21
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor Dac Pham, Atsushi Kameyama, J. Keaty, EngineeringVlsi DesignHigh Frequency DesignComputer ArchitectureProcessor Architecture	2006	15

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