The circuit and physical design of the POWER4 microprocessor

TLDR

The IBM POWER4 processor is a 174‑million‑transistor chip running above 1.3 GHz with two cores, high‑speed buses, and on‑chip memory, whose size and high frequency posed significant design challenges. This paper describes the circuit and physical design of POWER4 and reports the results achieved. The design methodology focused on clock distribution, circuits, power, integration, and timing to meet project goals and finish on schedule. The design was completed on schedule, validating the methodology and demonstrating the feasibility of the complex, high‑frequency chip.

Abstract

The IBM POWER4 processor is a 174-million-transistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multi-site design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.