A 100 MHz 4 Mb cache DRAM with fast copy-back scheme

Abstract

A 4-Mb cache DRAM (CDRAM) which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM is described. The 4-Mb CDRAM features 100-MHz cache hit operation with an improved localized cache architecture. Circuits require only 7% more area than a conventional 4-Mb DRAM. There is 3* faster cache miss access over conventional copy back with fast copy back, as well as maximized mapping flexibility (applicable to direct mapping, set-associative, and full-associative). The block diagram of the 4-Mb CDRAM is shown along with a micrograph.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>