EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSystem-on-chip DesignCachingDirect Memory AccessMemory HierarchyMemory Hierarchy DesignMemory ManagementMemory Subsystem DesignCache DesignCache Memory DesignMain Memory Organization
This paper describes a concurrent operating cache DRAM (CDRAM) for low cost multi-media systems, in which the program and graphic data coexist in the main memory. The concurrent operation of the DRAM and SRAM completely removes the idle cycles. As a result, the average access time is equal to the SRAM access time of 6.5 ns with 0.6 /spl mu/m CMOS process. The flash write and direct read/write are also useful for the multi-media systems.
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500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface
N. Kushiyama, Shigeo Ohshima, D. Stark et al. · 2003 · 24 citations
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme
K. Dosaka, Y. Konishi, K. Hayano et al. · IEEE Journal of Solid-State Circuits · 1992 · 19 citations