N. Kushiyama

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Osamu Hirabayashi, Atsushi Kawasumi, Akira Suzuki et al. · 2009 · 92 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 500-megabyte/s data-rate 4.5 M DRAM

N. Kushiyama, Shigeo Ohshima, D. Stark et al. · IEEE Journal of Solid-State Circuits · 1993 · 42 citations

Engineering, Computer Engineering, Electrical Engineering +13

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

Takashi Ohsawa, T. Furuyama, Yoshihiro Watanabe et al. · IEEE Journal of Solid-State Circuits · 1987 · 26 citations

Engineering, Electrical Engineering, Low-power Design +16

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

N. Kushiyama, Shigeo Ohshima, D. Stark et al. · 2003 · 24 citations

Engineering, Computer Engineering, Computer Science +15

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

S. Takase, N. Kushiyama · IEEE Journal of Solid-State Circuits · 1999 · 23 citations

Engineering, Computer Engineering, Computer Science +17