S. Takase

A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Tz-yi Liu, Tian Hong Yan, R.E. Scheuerlein et al. · IEEE Journal of Solid-State Circuits · 2013 · 177 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 130.7mm<sup>2</sup> 2-layer 32Gb ReRAM memory device in 24nm technology

Tz-yi Liu, Tian Hong Yan, R.E. Scheuerlein et al. · 2013 · 117 citations

Engineering, Computer Engineering, Electrical Engineering +9

A 500-megabyte/s data-rate 4.5 M DRAM

N. Kushiyama, Shigeo Ohshima, D. Stark et al. · IEEE Journal of Solid-State Circuits · 1993 · 42 citations

Engineering, Computer Engineering, Electrical Engineering +13

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

N. Kushiyama, Shigeo Ohshima, D. Stark et al. · 2003 · 24 citations

Engineering, Computer Engineering, Computer Science +15

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

S. Takase, N. Kushiyama · IEEE Journal of Solid-State Circuits · 1999 · 23 citations

Engineering, Computer Engineering, Computer Science +17