Memory Controller Design
Memory Controller Design is a specialized subsystem architecture within computer memory systems that orchestrates data flow and timing between processors and memory units by managing access protocols, arbitration, error handling, and command scheduling to optimize performance, power efficiency, and reliability.
298
Publications
15.9K
Citations
1K
Authors
256
Institutions
Publications per year
2017–2026
54
Parents
298
The design and implementation of a first-generation CELL processor
D. Pham, S. Asano, M. Bolliger et al. · 2005 · 547 citations
Engineering, Computer Engineering, Electrical Engineering +17
Jamie Liu, Ben Jaiyen, Richard Veras et al. · ACM SIGARCH Computer Architecture News · 2012 · 449 citations
Self-Optimizing Memory Controllers
Engin İpek, Onur Mutlu, José F. Martínez et al. · ACM SIGARCH Computer Architecture News · 2008 · 371 citations
1–5 of 298
1K
18
h-index
11
h-index
11
h-index
9
h-index
6
h-index
1–5 of 1K
256
Intel (United States)
Santa Clara, United States
14 h-index
41 publications
3.1K citations
Carnegie Mellon University
Pittsburgh, United States
14 h-index
48 publications
8.2K citations
Eindhoven University of Technology
Eindhoven, The Netherlands
11 h-index
23 publications
663 citations
The University of Texas at Austin
Austin, United States
11 h-index
24 publications
2.5K citations
University of Utah
Salt Lake City, United States
10 h-index
47 publications
4.9K citations

Cornell University
Ithaca, United States
10 h-index
28 publications
2.9K citations
Universitat Politècnica de Catalunya
Barcelona, Spain
9 h-index
39 publications
1.5K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
8 h-index
25 publications
1.6K citations
1–8 of 256
14 publications · 1.6K citations
14
h-index
11 publications · 669 citations
11
h-index
9 publications · 398 citations
9
h-index
7 publications · 742 citations
7
h-index
6 publications · 312 citations
6
h-index
1–5