Page placement in hybrid memory systems

TLDR

Phase‑Change Memory offers high density and low idle power but slower access and limited endurance, prompting hybrid DRAM‑PCM designs. The study proposes a hybrid memory architecture featuring a hardware‑driven page placement policy. The policy uses the memory controller to track access patterns, migrate pages between DRAM and PCM, and translate addresses, with the operating system periodically updating page mappings. Simulations of 27 workloads demonstrate that the design is more robust and achieves lower energy‑delay² than existing hybrid systems.

Abstract

Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byte-addressable and exhibits access times in the nanosecond range, it can be used in main memory designs. In fact, PCM has higher density and lower idle power consumption than DRAM. Unfortunately, PCM is also slower than DRAM and has limited endurance. For these reasons, researchers have proposed memory systems that combine a small amount of DRAM and a large amount of PCM. In this paper, we propose a new hybrid design that features a hardware-driven page placement policy. The policy relies on the memory controller (MC) to monitor access patterns, migrate pages between DRAM and PCM, and translate the memory addresses coming from the cores. Periodically, the operating system updates its page mappings based on the translation information used by the MC. Detailed simulations of 27 workloads show that our system is more robust and exhibits lower energy-delay2 than state-of-the-art hybrid systems.