1993 · 49 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceFault-tolerant ComputingFault-tolerant SystemsBuilt-in Self-testDesign For TestabilityAutomatic Test Pattern GenerationCombinational Logic DesignCombinational Logic SynthesisMinimal SetsStuck-at Fault Testing
Article Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits Share on Authors: Seiji Kajihara View Profile , Irith Pomeranz View Profile , Kozo Kinoshita View Profile , Sudhakar M. Reddy View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 102–106https://doi.org/10.1145/157485.164617Online:01 July 1993Publication History 45citation336DownloadsMetricsTotal Citations45Total Downloads336Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
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Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations