2007 · 138 citations · 25 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignLeakage Power ReductionLow-power Digital Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsPower ManagementPower OptimizationCmos Logic CircuitsCmos Logic DesignLeakageLeakage-constrained Circuit DesignLow-power Cmos DesignLow-power Logic DesignPower ConsumptionPower Consumption Optimization
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logic style is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.
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Device scaling limits of Si MOSFETs and their application dependencies
D.J. Frank, R.H. Dennard, E. Nowak et al. · Proceedings of the IEEE · 2001 · 1.6K citations
Engineering, Computer Engineering, Electrical Engineering +17
E. Nowak, I. Aller, Thomas Ludwig et al. · IEEE Circuits and Devices Magazine · 2004 · 387 citations
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Getting to the bottom of deep submicron
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Subthreshold leakage modeling and reduction techniques
James Kao, S. Narendra, Anantha P. Chandrakasan · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2002 · 267 citations
Engineering, Computer Engineering, Electrical Engineering +17