2003 · 45 citations · 9 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsMicrowave EngineeringCmos Circuit DesignIntegrated Circuit DesignMicrowave Integrated CircuitsMicrowave Semiconductor DevicesPower DividersRadio-frequency Integrated CircuitsCompact Power DividersPower ConsumptionPower Consumption ModelingPower Consumption OptimizationPower-efficient ArchitectureRadio-frequency Integrated Circuit DesignRf Cmos Design
A 2:1 static frequency divider was fabricated in a 0.12-/spl mu/m SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.
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Substrate crosstalk reduction using SOI technology
Jean‐Pierre Raskin, A. Viviani, Denis Flandre et al. · IEEE Transactions on Electron Devices · 1997 · 292 citations
SOI technology for the GHz era
G. Shahidi · IBM Journal of Research and Development · 2002 · 192 citations
Engineering, Computer Engineering, Electrical Engineering +13
Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits
N. Zamdmer, Jean‐Olivier Plouchart, J. Kim et al. · 2002 · 37 citations