2002 · 64 citations · 26 references
EngineeringComputer EngineeringComputer ScienceFault-tolerant ComputingMicroelectronicsSystem-on-chip DesignBuilt-in Self-testDesign For TestabilityDigital Integrated Circuit DesignDigital Logic DesignLogic SynthesisMixed-signal Integrated Circuit DesignAutomatic Test Pattern GenerationDesign For ScanabilityDeterministic Test Pattern GenerationFault CoverageFault Coverage AnalysisOn-chip Test Pattern GenerationScan Chain DesignScan Design
A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.
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Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations
Built-in test for VLSI: Pseudorandom techniques
Integration · 1989 · 866 citations
Engineering, Computer Engineering, Electrical Engineering +12
LFSR-coded test patterns for scan designs
B. Koenemann · Medical Entomology and Zoology · 1991 · 510 citations