ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technology

Abstract

A modified double-poly NMOS technology is proposed, providing CMOS structures. The P-channel transistors are made in the second poly layer. The process scheme is standard, except for the laser annealing step. A method of laser annealing of processed [even non-planar] samples is derived, giving rise to a concept of selective annealing. Hole mobility up to 120 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V.S, was reached in the polysilicon transistors. The characteristics of the bulk N-channel transistors are kept unmodified by laser exposure.