A hardware approach to self-testing of large programmable logic arrays

Abstract

A hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8 \times 16 \times 8</tex> PLA is completely tested within 52 cycles; a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16 \times 48 \times 8</tex> PLA requires 132 cycles. The test patterns do not depend on the individual personalization of any PLA. So there is no more need of an extensive fault simulation or test pattern computation. The result is a fast efficient built-in test for PLA-macros, the most promising building blocks of VLSI circuits.