Concepedia

An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC

Younes Lahbib, R. Kamdem, Mohamed-lyes Benalycherif, Rached Tourki

Computers & Electrical Engineering · 2005 · 11 citations · 18 references

Concepts

EngineeringComputer EngineeringComputer ScienceHardware Description LanguagesSystem-on-chip DesignSystems ModelingAssertion-based VerificationBuilt-in Self-testFinite State Machine ModelingHardware Modeling For Digital SystemsModel ExecutionModel TransformationAssertionsControl-path AssertionsHardware Assertion LanguagesHardware VerificationRegister-transfer Level AssertionsSystem-level ModelingSystemc Modeling

References

18

The temporal logic of programs

Amir Pnueli · 1977 · 5.7K citations

Computing, Computer Science, Formal Methods +16

The model checker SPIN

Gerard J. Holzmann · IEEE Transactions on Software Engineering · 1997 · 3.8K citations

Computing, Computer Engineering, Computer Science +12

System-level design: orthogonalization of concerns and platform-based design

Kurt Keutzer, A. Richard Newton, Jan M. Rabaey et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2000 · 966 citations

Engineering, Computer Engineering, Computer Science +17

Symbolic Model Checking

J. Barry Cooke · Microprocessors and Microsystems · 1994 · 215 citations

Smart simulation using collaborative formal and simulation engines

Pei Hsin Ho, Thomas R. Shiple, Kevin Harer et al. · 2000 · 125 citations

Computing, Computer Engineering, Computer Science +15