Control-path Assertions

Control-Path Assertions is a formal verification methodology that specifies and checks temporal properties governing the sequencing and branching behavior of control logic in hardware designs, distinguishing it from data-path assertions by focusing on control flow correctness rather than data transformations.

11

Publications

428

Citations

27

Authors

17

Institutions

Publications per year

2017–2026

0

Authors

27

  1. BM
    B.T. Murray

    University of Michigan, United States

    1 publications · 152 citations

    1

    h-index

  2. HA
    Hasan Amjad

    University of Cambridge, United Kingdom

    1 publications · 18 citations

    1

    h-index

  3. JS
    Joseph Sifakis

    Verimag, France

    1 publications · 18 citations

    1

    h-index

  4. CH
    Chung-Yang Huang

    National Taiwan University, Taiwan

    1 publications · 38 citations

    1

    h-index

  5. KI
    Kei Imafuku

    Nara Institute of Science and Technology, Japan

    1 publications · 20 citations

    1

    h-index

1–5 of 27

Venues

  1. Communications of the ACM

    1 publications · 72 citations

    1

    h-index

  2. Electronic Notes in Theoretical Computer Science

    ENTCS · 1 publications · 18 citations

    1

    h-index

  3. Journal of Electronic Testing

    JETTA · 1 publications · 18 citations

    1

    h-index

  4. Acta Informatica

    1 publications · 18 citations

    1

    h-index

  5. Formal Aspects of Computing

    1 publications · 37 citations

    1

    h-index

1–5