Systemc Modeling
SystemC Modeling is a hardware modeling methodology that uses the SystemC library, a C++-based language extension, to enable high-level simulation and verification of digital systems through discrete-event simulation, distinguishing itself by integrating transaction-level modeling with precise timing behavior for heterogeneous system design.
452
Publications
13K
Citations
965
Authors
286
Institutions
Publications per year
2017–2026
25
452
Preeti Ranjan Panda · 2001 · 188 citations
Analyzing On-Chip Communication in a MPSoC Environment
2004 · 147 citations
1–5 of 452
965
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286
University of Verona
Verona, Italy
17 h-index
76 publications
2.1K citations
University of Bremen
Bremen, Germany
17 h-index
78 publications
1.8K citations

University of Tübingen
Tübingen, Germany
13 h-index
48 publications
1.1K citations
STMicroelectronics (Switzerland)
Geneva, Switzerland
12 h-index
25 publications
1.1K citations
STMicroelectronics (France)
Montrouge, France
12 h-index
22 publications
1.4K citations
Politecnico di Milano
Milan, Italy
12 h-index
32 publications
856 citations

Universidad de Cantabria
Santander, Spain
12 h-index
46 publications
1.2K citations

Sorbonne Université
Paris, France
11 h-index
42 publications
1K citations
1–8 of 286
Conference · 19 publications · 566 citations
14
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11 publications · 353 citations
11
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9 publications · 276 citations
9
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Conference · 7 publications · 265 citations
7
h-index
7 publications · 290 citations
7
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