Systemc Modeling

SystemC Modeling is a hardware modeling methodology that uses the SystemC library, a C++-based language extension, to enable high-level simulation and verification of digital systems through discrete-event simulation, distinguishing itself by integrating transaction-level modeling with precise timing behavior for heterogeneous system design.

452

Publications

13K

Citations

965

Authors

286

Institutions

Publications per year

2017–2026

25

Authors

965

  1. RD
    Rolf Drechsler

    University of Bremen, Germany

    34 publications · 782 citations

    18

    h-index

  2. FF
    Franco Fummi

    University of Verona, Italy

    23 publications · 627 citations

    14

    h-index

  3. EV
    Eugenio Villar

    Universidad de Cantabria, Spain

    13 publications · 386 citations

    12

    h-index

  4. WR
    Wolfgang Rosenstiel

    University of Tübingen, Germany

    13 publications · 363 citations

    12

    h-index

  5. HP
    Hiren Patel

    University of Waterloo, Canada

    11 publications · 288 citations

    11

    h-index

1–5 of 965

Venues

  1. Design, Automation, and Test in Europe

    Conference · 19 publications · 566 citations

    14

    h-index

  2. 11

    h-index

  3. Design Automation for Embedded Systems

    9 publications · 276 citations

    9

    h-index

  4. 7

    h-index

  5. 7

    h-index

1–5