2005 · 238 citations · 13 references
EngineeringComputer EngineeringComputer ScienceComputer NetworksLow-power DesignSystem-on-chip DesignDelay ModelingInterconnect ArchitectureInterconnect DesignLatency OptimizationNetwork ArchitectureNetwork-on-chip DesignDelay-insensitive CircuitsLow-latency DesignLow-latency InterconnectsNetwork-on-chipNetwork-on-chip ArchitecturesScalable InterconnectsSystemc ModelingThroughput
Scalable, low‑latency, power‑efficient SoC interconnects cannot be satisfied solely by point‑to‑point or shared‑bus designs. The paper proposes a new asynchronous NOC architecture that delivers low‑latency transfers. The architecture is a GALS system of synchronous islands linked by a delay‑insensitive asynchronous NOC topology, with a protocol and implementation presented in SystemC and transaction‑level modeling. Simulations show the asynchronous NOC achieves 5 GB/s throughput in a 0.13 µm CMOS process.
The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a delay insensitive asynchronous network-on-chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling. Preliminary simulation results show that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 /spl mu/m CMOS technology.
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Chain: a delay-insensitive chip area interconnect
John Bainbridge, Steve Furber · IEEE Micro · 2002 · 225 citations
Engineering, Computer Engineering, Electrical Engineering +14
The VLSI-programming language Tangram and its translation into handshake circuits
Kees van Berkel, J. Kessels, Marly Roncken et al. · 1991 · 161 citations