An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework

TLDR

Scalable, low‑latency, power‑efficient SoC interconnects cannot be satisfied solely by point‑to‑point or shared‑bus designs. The paper proposes a new asynchronous NOC architecture that delivers low‑latency transfers. The architecture is a GALS system of synchronous islands linked by a delay‑insensitive asynchronous NOC topology, with a protocol and implementation presented in SystemC and transaction‑level modeling. Simulations show the asynchronous NOC achieves 5 GB/s throughput in a 0.13 µm CMOS process.

Abstract

The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a delay insensitive asynchronous network-on-chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling. Preliminary simulation results show that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 /spl mu/m CMOS technology.