Assertions

An assertion is a formal syntactic construct in VHDL testbenches that specifies run-time conditions to detect and report violations during simulation, thereby serving as a verification mechanism within error handling by instantiating a monitored predicate on signal behavior.

775

Publications

42.4K

Citations

1.6K

Authors

608

Institutions

Publications per year

2017–2026

117

Authors

1.6K

  1. PN
    P. N. Johnson‐Laird

    Princeton University, United States

    10 publications · 750 citations

    10

    h-index

  2. SV
    Shobha Vasudevan

    University of Illinois Urbana-Champaign, United States

    9 publications · 434 citations

    9

    h-index

  3. SK
    Sangeet Khemlani

    United States Naval Research Laboratory, United States

    7 publications · 450 citations

    7

    h-index

  4. GP
    Graziano Pravadelli

    University of Verona, Italy

    7 publications · 240 citations

    7

    h-index

  5. RB
    Robert Bruce Findler

    University of Utah, United States

    6 publications · 637 citations

    6

    h-index

1–5 of 1.6K

Venues

  1. ACM SIGPLAN Notices

    12 publications · 400 citations

    11

    h-index

  2. IEEE Transactions on Software Engineering

    TSE · 12 publications · 541 citations

    10

    h-index

  3. SSRN Electronic Journal

    Repository · 7 publications · 157 citations

    7

    h-index

  4. Electronic Notes in Theoretical Computer Science

    ENTCS · 6 publications · 543 citations

    6

    h-index

  5. The Philosophical Review

    5 publications · 345 citations

    5

    h-index

1–5