Vhdl Syntax

VHDL Syntax is the formal set of grammatical rules and structural constraints of the VHDL hardware description language that govern the correct formation and arrangement of its lexical tokens and constructs (such as entities, architectures, declarations, and statements) independently of their semantic interpretation.

94

Publications

3.2K

Citations

218

Authors

111

Institutions

Publications per year

2017–2026

4

Authors

218

  1. EC
    E. Christen

    Analog Devices (United States), United States

    3 publications · 352 citations

    3

    h-index

  2. MK
    Matthijs Kooijman

    University of Twente, Netherlands

    3 publications · 112 citations

    3

    h-index

  3. ME
    Marco E. T. Gerards

    University of Twente, Netherlands

    3 publications · 112 citations

    3

    h-index

  4. CB
    Christiaan Baaij

    University of Twente, Netherlands

    3 publications · 112 citations

    3

    h-index

  5. MS
    Moe Shahdad

    Photometrics (United States), United States

    3 publications · 97 citations

    3

    h-index

1–5 of 218

Venues

  1. IEEE Design & Test of Computers

    5 publications · 207 citations

    5

    h-index

  2. European Design Automation Conference

    Conference · 4 publications · 85 citations

    4

    h-index

  3. Microelectronics Journal

    3 publications · 144 citations

    3

    h-index

  4. Microprocessors and Microsystems

    MICPRO · 3 publications · 106 citations

    3

    h-index

  5. Formal Methods in System Design

    3 publications · 40 citations

    3

    h-index

1–5