Conditional Signal Assignment

Conditional Signal Assignment is a concurrent signal assignment statement in VHDL that belongs to the class of data-flow modeling constructs, distinguished by its evaluation of Boolean conditions to determine the value assigned to a target signal, with each condition sequentially assessed until the first true condition is encountered.

8

Publications

291

Citations

26

Authors

13

Institutions

Publications per year

2017–2026

0

Authors

26

  1. RJ
    R. Jacob Vogelstein

    Johns Hopkins University, United States

    1 publications · 62 citations

    1

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  2. RG
    Reinhard Gerhards

    Ruhr University Bochum, Germany

    1 publications · 14 citations

    1

    h-index

  3. HD
    H. Duddeck

    Leibniz University Hannover, Germany

    1 publications · 14 citations

    1

    h-index

  4. DJ
    Damien Jeannerat

    University of Geneva, Switzerland

    1 publications · 14 citations

    1

    h-index

  5. TM
    Tristan Mary‐Huard

    AgroParisTech, France

    1 publications · 27 citations

    1

    h-index

1–5 of 26

Venues

  1. Experimental Brain Research

    1 publications · 81 citations

    1

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  2. 1

    h-index

  3. Journal of Magnetic Resonance (1969)

    1 publications · 14 citations

    1

    h-index

  4. Proceedings of the IEEE

    1 publications · 62 citations

    1

    h-index

  5. Magnetic Resonance in Chemistry

    MRC · 1 publications · 14 citations

    1

    h-index

1–5