Case Statements

Case Statements is a conditional control structure in VHDL syntax that belongs to the class of sequential statements and is distinguished by its evaluation of a single expression against multiple discrete alternatives to determine which branch of code to execute.

10

Publications

330

Citations

21

Authors

15

Institutions

Publications per year

2017–2026

0

Authors

21

  1. CC
    Cristina Cifuentes

    The University of Queensland, Australia

    2 publications · 110 citations

    2

    h-index

  2. NM
    Noah Mendelsohn

    University of Washington, United States

    1 publications · 19 citations

    1

    h-index

  3. MV
    M. Van Emmerik

    The University of Queensland, Australia

    1 publications · 63 citations

    1

    h-index

  4. JN
    James Noble

    Victoria University of Wellington, New Zealand

    1 publications · 29 citations

    1

    h-index

  5. DM
    David McAllester

    Toyota Technological Institute at Chicago, United States

    1 publications · 17 citations

    1

    h-index

1–5 of 21

Venues

  1. Software Practice and Experience

    3 publications · 79 citations

    3

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  2. Library & Information Science Research

    1 publications · 17 citations

    1

    h-index

  3. Science of Computer Programming

    1 publications · 47 citations

    1

    h-index

  4. ACM SIGPLAN Notices

    1 publications · 62 citations

    1

    h-index

1–4