Case Statements
Case Statements is a conditional control structure in VHDL syntax that belongs to the class of sequential statements and is distinguished by its evaluation of a single expression against multiple discrete alternatives to determine which branch of code to execute.
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2017–2026
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A nesting level complexity measure
Paul Piwowarski · ACM SIGPLAN Notices · 1982 · 62 citations · Full text
Michael Homer, James Noble, Kim B. Bruce et al. · 2012 · 29 citations
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Toyota Technological Institute at Chicago, United States
1 publications · 17 citations
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The University of Queensland
Brisbane, Australia
2 h-index
4 publications
220 citations
Stanford University
Stanford, United States
1 h-index
2 publications
38 citations
University of California, Riverside
Riverside, United States
1 h-index
1 publications
17 citations
University of Cambridge
Cambridge, United Kingdom
1 h-index
1 publications
16 citations
IBM (United States)
Armonk, United States
1 h-index
1 publications
39 citations
Nokia (United States)
Coppell, United States
1 h-index
1 publications
17 citations
Cranfield University
Cranfield, United Kingdom
1 h-index
2 publications
32 citations

Victoria University of Wellington
Wellington, New Zealand
1 h-index
3 publications
87 citations
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3 publications · 79 citations
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1 publications · 17 citations
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1 publications · 47 citations
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1 publications · 62 citations
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