Aliases

An Alias is a syntactic construct in VHDL that associates an alternative identifier with a named entity, such as a signal, variable, constant, or subprogram, thereby providing a shorthand or mnemonic reference to the original entity within a declarative region.

108

Publications

7K

Citations

482

Authors

204

Institutions

Publications per year

2017–2026

17

Authors

482

  1. BG
    Barbara G. Ryder

    Rutgers, The State University of New Jersey, United States

    7 publications · 990 citations

    7

    h-index

  2. WL
    William Landi

    Rutgers, The State University of New Jersey, United States

    6 publications · 942 citations

    6

    h-index

  3. SX
    Sean X. Zhang

    Johns Hopkins University, United States

    3 publications · 281 citations

    3

    h-index

  4. PC
    Paul Carini

    SUNY New Paltz, United States

    3 publications · 627 citations

    3

    h-index

  5. FJ
    Fredrik Johansson

    Swedish Defence Research Agency, Sweden

    3 publications · 99 citations

    3

    h-index

1–5 of 482

Venues

  1. 9

    h-index

  2. ACM SIGPLAN Notices

    5 publications · 425 citations

    5

    h-index

  3. 3

    h-index

  4. The Astrophysical Journal

    ApJ · 2 publications · 381 citations

    2

    h-index

  5. Nucleic Acids Research

    2 publications · 234 citations

    2

    h-index

1–5