A CMOS Structure with high latchup holding voltage

Abstract

Latchup free operation is demonstrated in CMOS by attaining holding voltages in excess of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> (5V). A thin epitaxial layer over a heavily doped substrate together with butted background contact at transistor sources is shown to be an effective structure to control the parasitic bipolar latchup. Experimental results are presented with and without butted contact and with different epi-thicknesses. In addition to the traditionally quoted latchup holding current, measurements of latchup holding voltage are provided allowing a more clearly defined determination of latchup immunity.