IEEE Electron Device Letters · 1983 · 84 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignIntegrated Circuit DevicesMetal-oxide-semiconductor Field-effect TransistorsSemiconductor HeterostructuresCmos Fabrication ProcessesEpitaxial MaterialsEpitaxial OverlayersLeakage Current Reduction
n-well guard rings have long been used for isolating potential electron injectors to avoid latch-up of CMOS circuits. Such guard rings are shown to be orders of magnitude more efficient for CMOS fabricated in an epitaxial layer (epi-CMOS) than for bulk (non-epi) CMOS. The maximum escape probability in epi-CMOS measures 3.9E-06 while for bulk CMOS it is 1.8E-02.
3
Elimination of latch up in bulk CMOS
Robert Payne, W.N. Grant, W.J. Bertram · 1980 · 58 citations
Engineering, Computer Engineering, Electrical Engineering +12