Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester

Abstract

This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A very fast transmission line pulsing (VF-TLP) tester is used to inject a disturbance into an IC under operation. A system failure criterion is chosen and a critical stress level is extracted. A modeling methodology is also developed to precisely describe each part of the set up and provide a complete model that describes the IC response to ESD indirect effects.